In a NAND flash memory, all or half the number of a plurality of cells connected to a selected word line are connected to the respective bit lines, and data writing or reading is performed collectively on all or half the number of cells (such as cells of 2-4 kB) arranged in a row direction collectively, using a latch circuit connected to the bit lines.
In a NAND flash memory, a threshold voltage of a memory cell is set to a negative value during an erase operation, and is set to a positive value when electrons are injected into the memory cell during a write operation. The erase operation is performed in block units (by the unit of 1 MB, for example) and all the cells included in a plurality of NAND strings are erased simultaneously (see Jpn. Pat. Appln. KOKAI Publication No. 2004-192789).
Since the threshold voltage becomes a large negative value after the erase operation, if the erasure is performed deeply, a stress is applied to the cell and degrades the cell. This results in deterioration in data retention properties. Accordingly, the erasure needs to be performed shallowly, such that the threshold voltage takes a negative value as small as possible. When erasure is performed shallowly, it is possible to perform the erasure little by little by making the erase voltage low and increasing the erase voltage gradually. In this case, however, since the erasure time increases and erasure pulses are applied to the cell many times, a stress is applied to the cell.
In order to suppress the number of times of over-erase and erasure and suppress deep erasure due to over-erase, the methods as will be described below have been proposed. The first proposal is an approach of performing soft erasure of erasing cells at a low erase voltage, counting the number of erased cells, setting an erase voltage according to the number of erased cells, and performing the next erase operation (see Jpn. Pat. Appln. KOKAI Publication No. 2002-25283, for example). The second proposal is an approach of performing a read operation a plurality of times by varying the verify level during soft erase verification after the soft erasure, examining the center of threshold voltage distribution, setting an erase voltage according to the level of the center of the threshold voltage distribution, and then performing the next erase operation (see Jpn. Pat. Appln. KOKAI Publication No. 2002-157890, for example). Furthermore, as a related technique, a semiconductor storage device capable of reducing the erasure time by reducing the number of times of erasure pulse application and thereby improving precision in erase verification has been proposed (see Jpn. Pat. Appln. KOKAI Publication No. 2009-163782, for example (hereinafter referred to as Patent Document 4)).
However, distribution of threshold voltages of memory cells after soft erasure is not constant, and is dependent upon distribution of data stored in the memory cells before the erasure. It is therefore difficult to precisely set the next erase voltage after the soft erasure and to precisely perform the erasure by reducing the erasure time, according to the above-described approaches. A demand is therefore made for a semiconductor memory device capable of precisely setting the next erase voltage after the soft erasure.